On Mon, 6 Oct 1997, Clay Cowgill wrote:
> I think Steve did that? Someone had a VHDL or Verilog model of it almost
> done. Was is Joe?
It was me. I've got one done in Verilog. I still haven't tested
it though, so I'm not guaranteeing anything. I'll try to put it in a
public place (my lame web page, for instance) in the next few days if
anyone's interested.
(BTW: Before anyone asks, I'm NOT doing a version in VHDL.
Masochism like that is definitely NOT my style....)
Joe
