> Actually I've been thinking about something.....
>
> Clay, what parts were you targeting to when you posted about your
>original adder? A Xilinx CLB can implement any function of 5 variables,
>so a 24 bit ripple-carry adder would take < 48 CLBs, which seems pretty
>reasonable to me. It might suck up a lot of routing resources, though...
I was synthesizing to the Cypress CY7C37x family. They're Complex
Programmable Logic Devices, not FPGA's like the Xilinx/Altera/Orca stuff.
They look pretty comparable to the Lattice 20xx and 30xx series.
Devices are available in 32, 64 and 128 "Macrocells". Each macrocell is
about like a 22V10's macrocell, but with more product terms coming in.
Your numbers look about right-- there just aren't as many macrocells
available as in an FPGA. (For Cypress a 24 bit ripple adder would take
about 168 product terms, 48 Macrocells, and 24 passes through the array
(ouch). A full-carry lookahead would eat more product terms-- ~300, and a
few more macrocells ~56, but take MUCH less time-- 6 passes through the
array.)
That's kinda why I'm trying to do this in VHDL-- so I can target either
FPGA or CPLD parts depending on what's needed. Xilinx has been publishing
numbers around $3 for their new slimmed-down 4000 series which would be
pretty cool. To keep things affordable I need to stay with a 32 or 64
macrocell device in a CPLD for now.
-Clay
Clayton N. Cowgill Engineering Manager
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